?߼?

SIGNAL sw1, sw1_r : STD_LOGIC := '0';

SIGNAL sw2, sw2_r : STD_LOGIC := '0';

SIGNAL sw3, sw3_r : STD_LOGIC := '0';

SIGNAL sw4, sw4_r : STD_LOGIC := '0';

SIGNAL status : STD_LOGIC := '0';

sw_proc: PROCESS(clk)

BEGIN

IF RISING_EDGE(clk) THEN

IF rst = '1' THEN

sw1_r <= '0';

sw2_r <= '0';

sw3_r <= '0';

sw4_r <= '0';

status <= '0';

ELSE

IF (sw1_r /= sw1) OR

(sw2_r /= sw2) OR

(sw3_r /= sw3) OR

(sw4_r /= sw4) THEN

status <= NOT status;

END IF;

------------------------

sw1_r <= sw1;

sw2_r <= sw2;

sw3_r <= sw3;

sw4_r <= sw4;

END IF;

END IF;

END PROCESS;